Dual speed pll using saa1057

[DJ Adam Eve]

Hello. I know Jan no longer really supports the saa1057 pll design posted on pira.cx, however. It is a very popular design and a lot of people have reposted it, and put links to it on their own sites.

As Jan already said on the old forum the saa is a pretty old chip that was designed originally for use with receivers not transmitters. However the pll works pretty well and locks on fast, it does allow (with a bit of modding) for you to use out of lock power down too. The code Jan wrote is fairly simple (apparently), but works well.
 
The problems I am having (others are to) is with there being a 1khz tone superimposed over the signal (clearly audible). I have used an opamp voltage follower at the output still have the noise. I have played about a little with the decoupling of the input and output amplifiers, I have also added 1n caps to the bus lines. Still I have the noise.

Jan: please help! Reading the datasheet of the saa1057 I have a few questions; do the data lines have constant activity on them? Could that be anything to do with it? I also notice you have to configure the pll to be dual speed, and the input/ output amps are configurable, could this beb anything to do with the problems? Where do you think the noise originates? Any help would be great.

Also I have done another pcb layout without the wire links you used, can I email it to you please?

[DJ Adam Eve]

OK, so I used my Oscilloscope and located the only sources of anything like 1khz on the pll, and think I have located it in the sample and hold circuits r & c decoupling pins.

I have started experiments with the values of components there. I tested last night and saw some improvements.

Any thoughts anyone?

[DJ Adam Eve]

OK... So i am making some very good progress with the saa057 PLL... I AM DETERMINED to get this working well and i have 100% confidence that it is possible.

I now need some help REALLY badly please; i don't do much code writing/programming (it's next on my 'to do' list). I have been looking at the firmware that Jan has provided for this circuit and notice it is version 5, is there any chance of viewing the change you made please Jan?

Also i want to locate within the code the data bits for configuration words A & B. I have been looking at the assembly file, is this the config bits?:


START   CLRWDT
        CLRF    PORTA
        CLRF    COUNT
        MOVLW   B'00100000'       
        MOVWF   WORKA
        MOVLW   B'00111010'
        MOVWF   WORKB

If it is i can't really see wahts going on beacsue the word should be 16 bit unless the last bit is set '0' (don't care), which it is, but the first bitshould be '1' shouldn't it? And shouldn't the second also be '1' to configure for FM?

Please, any help would be great. The .ASM file is attached in case anyone fancies a look and hasn't got a copy.

[Jan]

It's about 15 years back when this piece of code has been written. Don't ask me for exact details as I really don't remember 

The configuration words A and B are filled bit by bit using the instructions numbered from ;0 to ;16
The configuration words are present twice in the code as they differ in charge pump current so higher current is used for first tuning and lower current is used for keeping the frequency tuned - that's the dual speed 
WORKA and WORKB holds a 16bit constant that is added to the value read from the DIP switches so the final frequency is computed.
There's also some repeated upload of the frequency in about 30 minutes intervals due to safety reasons and reliability improvement.

If you have some PCB design for this PLL, please create also a black&white output that can be used directly for home PCB manufacturing. If you convert that images into gif or png format, they will be small in size so you'll be able to post them to this forum.

The SAA1057 PLL has a disadvantage in the internal phase comparator frequency which is 1 kHz. Unfortunatelly that frequency can be easily audible as ears are very sensitive to 1 kHz. This should not occur in perfect design but often some 1 kHz residues may be present in the audio, especially due to ground loops and RF field going into the PLL circuit. There never has been a simple method, how to solve it. It was about a luck a bit, and hours of experimenting with wires, rf part and PLL block placement.

[DJ Adam Eve]

Hi Jan,

Thanks for the advice, i am now looking at the code, and i see the changes in charge pump current, that is what i was going to look at!

It actually appears that the config. (word B) goes to the PLL three times throughout the routine, is that right? The current seems to be: 2.3 @ start up then 0.07 for the second two cycles. I have noticed though that SLA load match is set 'asynchronuos' then 'synchronous' then 'asyncronous', is that relevant?

I put a Opamp voltage follower on the output of the PLL, but unfortunately it also replicates the AC part of the signal (the 1KHz tone).

Can you please tell me how you arrived at the values for the input/output of the output amplifier (the 4k7,10u tan, 10k and 0.47u)? In the datasheet it says 'Depends on tuner diode characteristics': Lots of the other designs out there have the same values, did you just use common values, or has everyone copied from you? The reason i ask is that I am using BB909 diodes and i was thinking about changing the output to form a low pass filter in an attempt to just pass the DC and filter off the HF AC tone, maybe a cutoff around 100hz? I have noticed that you can change the audible tone by playing with these values, i would like to get rid of it.

I have had my oscillscope on pins 1,2,3 of the device and see a clean wave at 1, then a distorted wave and highly distorted wave at 2 and 3. I have had some success playing around at TR, TCA and TCB; reducing the value of TR and decoupling TCB to gnd via a low value resistor, this seems to reduce the phase noise a bit.

I don't think i have grounding/RF issues becasue i have payed around with layouts so much, i have a solid ground plane, the DC is fed through chokes and the supply is smooth and well decoupled.

I really appriciate your help and if i find the answers to this little problem i will let you know so you can post them (if you would like to).

Thanks

[DJ Adam Eve]

I have decide to upload my own PCB layout for the PLL that Pira (Jan) designed.

This first post includes the PCB lauyout including component IDs.

you will notice i have included an extra decoupling capacitor at the DC input, as well as the 47k optional resistor at the PLL output.

I have dropped the wire links Jan used and allowed for pin connections should you want to use them.

The PCB is 45x50mm (HxW)

You will need to use my own look up chart for the frequency becasue the pin layout has changed, apart from that the design is the property of Pira.cz and should not be used comemrcially without permission.

For the hex, PCB pattern and frequency look up see next few posts.

NOTE: THE PCB PATTEREN IS REVERSED FOR TONER TRANSFER METHOD OF PCB FABRICATION, FOR UV EXPOSURE METHOD MAKE SURE THAT THE PATTERN IS ORIENTATED CORRECTLY (THE TEXT SHOULD READ CORRECTLY ON THE PCB ITSELF)

[DJ Adam Eve]

PCB file

45x50mm (HxW)

[DJ Adam Eve]

Here is the (pira) hex code and my own frequency look up.

You MUST use my look up if you used my layout.

GOOD LUCK!

[Jan]

As I remember the SAA1057 datasheet was extremely miserable. Moreover there are some differences between SAA1057 produced by Phillips and ST. That's probably the reason why the words are sent more times to the IC: 1) there's no information at all how to do it, 2) this has worked.
How the part values have been found, I really don't know today.

[DJ Adam Eve]

Oh yeah I have confidence that this pll can work well with your code. Its just a case of figuring out how to filter the output without loading it too much, either that or isolating the pll completely. I will keep you informed. Thanks

[DJ Adam Eve]

OK... Made some good progress over the weekend.... I probably should state (as i haven't before) that i am using this with my own oscillator/buffer design, and the 2n4427 output design by BW.

I have noticed that Jan fed the PLL signal into the collector in his design, i'm mixing the audio and PLL signal at the VCD and feeding it into the base of an MPSH10 oscillator (NOT the BW type). It may be that this method introduces even MORE noise than Jan's design.

Anyone following this thread please note; there are MUCH better PLL chips out there, the 1057 was designed for 80's fm receivers, look at the date on the datasheet!! Jan himself offers good code and support for a TSA5511 design (lift  it from his 5w tx design to use with other exciters), it also offers momentary push button tuning and LCD display. THere are a few designs for the SAA1057 which also have push button tuning and LCD (Freedo's/Salt and Light/15w multiplex), but ALL will suffer from the same noise problem. There are a couple of Spanish designs which use Jan's PLL and the RDVV oscillator/output which look like they have made some good progress toward minimising the sound by removing the decoupling cap from TCB, however this may lead to stability problems becasue of stray capacitance in the sample and hold circuit.

The secret is definately in the way the control voltage is filtered and used. I am using a voltage follower to isolate the control voltage from the PLL chip itself, this allows me much more scope to play with filter values. I have also changed Jan's code to up the output amp current, something which i THINK Jan reduced in an effort to minimise the noise and current consumption.

I am getting there... slowly!

I will upload pictures of my prototype exciter later.

[DJ Adam Eve]

OK, If you are at all interested in using my layout you might wnat to wait for a couple of days and i will upload a new image with my additions (which  hopefully reduce the noise to an acceptable level). Failing  that you can always surface mount extra comonents (there's only 3).

[DJ Adam Eve]

Please see attache an excel spreadsheet used for looking up frequency using my layout... Pretty straight forward: Either look up frequency on chart OR select from drop down menau and switch setting automatically generated in box on right.

If using open office not that drop down MIGHT not work, in which case simply enter the desired frequency in box.

[Eladi]

 Perhaps it would be a good idea insert a choke (low pass audio filter let only pass frequencies below 50 hz.) in vco voltage control that stops the 1khz noise.

 We would have in this way the vco voltage control that don't change so quickly for be interfered for the bf choke.

 It's only an idea don't checked for me. I like the simplicity of this pll design, specially with the programmed chip because unfortunately there is many circuits diagrams publicated but most of them don't publicates the PICs code.

 Sorry for my poor english. Best Regards.

[Will]

Hello, I've just want to say that I've never had this problem your getting, I know that does help much, But I remember the First one I built did have a similar problem but this was due to the coupling capacitor  or C5 on the schematic being either not present to to low.  You can use greater value which will suppress this but I would recommend changing your varicap diodes to ones that have a smaller Capacitor scale i.e 1-10pf instead ones that are 1-40pf for example.

I dont now how you building these either, If your etched your own PCB or even the Pira template I recommend building these as a ( Birds nest or Spider wiring as some call it ) on copper clad board with a good solid ground plane with the components floating about 6mm  above the ground plane. this is a must for me as I build 150watt rigs using the SAA1057 in the same way as I described with no problems at all.

If you want help just email me on Junction@gmx.co.uk I'm more than happy to help and show you pictures of one I've built this way.

Regards

Will