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Topic Summary

Posted by: duivenmelker
« on: October 16, 2012, 01:48:47 am »

here the transmitter as proven to work with the pira pll.
note: the 40p tuning capacitor may be removed when following the method as desribed in my former post.

Posted by: duivenmelker
« on: October 16, 2012, 01:28:37 am »

p.s. perhaps the varicap should get the highest possible voltage on 88 MHz. It was a long time ago i built transmitters and don't know for sure if varicap diodes increase of decrease in capacity when voltage is increased. However this is easily figured out by the given fact that at a lower frequency a higher tuning capacity is needed, so when comparing tuning voltages both on a high and on a low frequency will let you know how the varicap is behaving.

the amplifier stages in this schematic i never used, always use no-tune wideband stages. taking the pll's rf input from after the first buffer using a 10p capacitor for coupling. as a buffer i could recommend the bfr91 using the following diagram.

http://www.3-mtr.info/sales/Amplifier%20NoTune%20Profline%20300mW/Amplfier%2010mWatt%20-%20300mWatt%20rev%20A%20-%2028-06-2006.pdf
Posted by: duivenmelker
« on: October 16, 2012, 01:17:59 am »

Posted by: duivenmelker
« on: October 16, 2012, 01:17:14 am »

[/img]

i have built many transmitters using this oscillator using a BF199 with a wideband varicap diode and without the tuning capacitor and the original design from pira. They all worked very well without 1 khz tone or instability. The pll could lock anything from 88 to 108 MHz without manually tuning.

The secret is to set the pll to 88 MHz and bend your oscillator coil in a way the tuning voltage is very low (the lower the better) using a volt meter over the pll's tuning output for measurement. Now, the pll is able to lock any frequency up to 108 MHz. When you don't set your oscillator up like this, the pll might face lack of tuning capacity and therefor failure of locking to the desired frequency.
Posted by: DJ Adam Eve
« on: May 18, 2012, 05:50:58 pm »

Right, not sure what you mean... This design has no up and down buttons, it has DIP switches? Also this circuit puts out no rf at all, its a pll. The saa1057 can go down to 1.8mhz, but not with this firmware, thats designed to FM broadcast band. Are you using AM or fm?

If this isn't a design related to the pll perhaps you should start another thread?

Good luck!
Posted by: shiva
« on: May 18, 2012, 04:27:41 pm »

i have build the pll circuit.
the freq wont change.
i've try to change the freq by pushing the up/down button but it just change a bit.
the output rf is about 1800khz and stays there.

any idea?
Posted by: DJ Adam Eve
« on: May 08, 2012, 05:38:27 pm »

Quote from: Will on April 16, 2012, 12:47:30 pm
Hello, I've just want to say that I've never had this problem your getting, I know that does help much, But I remember the First one I built did have a similar problem but this was due to the coupling capacitor  or C5 on the schematic being either not present to to low.  You can use greater value which will suppress this but I would recommend changing your varicap diodes to ones that have a smaller Capacitor scale i.e 1-10pf instead ones that are 1-40pf for example.

I dont now how you building these either, If your etched your own PCB or even the Pira template I recommend building these as a ( Birds nest or Spider wiring as some call it ) on copper clad board with a good solid ground plane with the components floating about 6mm  above the ground plane. this is a must for me as I build 150watt rigs using the SAA1057 in the same way as I described with no problems at all.

If you want help just email me on Junction@gmx.co.uk I'm more than happy to help and show you pictures of one I've built this way.

Regards

Will

I'm glad you never had this issue, but LOTS of people have, including the chip manufacturer Phillips. If you search hard enough there is an AN out ther regarding the possibility of phase noise entering the PLL charge pump. THis is due to the internal architecture of the chip itself.

Reducing the current has helped a little, as did playing around with the sample and hold circuitary.

Oscillator type also has a massive bearing on outcome, maybe you have just luckily ended up with the right oscillator?!

Changing layout has little effect, the noise is NOT picked up through tracks, or components but rather originate INSIDE THE PLL chip itself.

As for spider wiring (Ugly bugging) a PLL circuit: I wouldn't recommend it if avoidable, certainly not as a way of improving performance over a proper PCB! It inherantly requires longer leads than through hole, therefor results are a lot less predictable in RF circuits. My alternative layout is on here somewhere, and that was the start of me getting this one working.

As for the varicaps: I couldn't comment. But the issue isn't with tuning, or with stability. It's phase noise, so i don't really see that a smaller varicap would help, but i will look into it (my understanding was that the diode's capacitance was dependant on the reverse voltage applied to it, therefor a BB809 and a BB109, or BB909 would all demonstrate a tuning capacitance of {for example} 10pf, just at different points on a voltage scale).


Thanks for your reply.
AE
Posted by: DJ Adam Eve
« on: May 08, 2012, 05:18:29 pm »

Quote from: Eladi on April 06, 2012, 04:26:47 am

 Perhaps it would be a good idea insert a choke (low pass audio filter let only pass frequencies below 50 hz.) in vco voltage control that stops the 1khz noise.

 We would have in this way the vco voltage control that don't change so quickly for be interfered for the bf choke.

 It's only an idea don't checked for me. I like the simplicity of this pll design, specially with the programmed chip because unfortunately there is many circuits diagrams publicated but most of them don't publicates the PICs code.

 Sorry for my poor english. Best Regards.

Yeah that's cool, thank for that reply. You may notice that else where in the forums is a post from me about this exact thing. Anyone else thinking about this fix would need to take in  to consideration the effect any capacitive element may have on the over all stability of the PLL (note the comment in Pira's original posting about not over loading the ouput with too much capacitance).

I have managed a work around for this.

ANyone thinking about this solution may consider a voltage follower at the PLL output.
Posted by: shiva
« on: May 05, 2012, 05:13:26 am »

Hi,
i'm new here (and in the rf world)
i just read this thread.
just noticed that this pll design produced 1khz noise.
hope you guys find a way to reduce the noise.

i've bought 10 pcs of saa1057 online and its on the way. planning to build AM PLL for my sdr radio.
i got the schematic from fred's web. it said covers 512KHz upto 32MHz.
that will do good.
anyone have ever bulid this project?
when i'm finished building my MW PLL i'll post it here


regards,
Posted by: Will
« on: April 16, 2012, 12:47:30 pm »

Hello, I've just want to say that I've never had this problem your getting, I know that does help much, But I remember the First one I built did have a similar problem but this was due to the coupling capacitor  or C5 on the schematic being either not present to to low.  You can use greater value which will suppress this but I would recommend changing your varicap diodes to ones that have a smaller Capacitor scale i.e 1-10pf instead ones that are 1-40pf for example.

I dont now how you building these either, If your etched your own PCB or even the Pira template I recommend building these as a ( Birds nest or Spider wiring as some call it ) on copper clad board with a good solid ground plane with the components floating about 6mm  above the ground plane. this is a must for me as I build 150watt rigs using the SAA1057 in the same way as I described with no problems at all.

If you want help just email me on Junction@gmx.co.uk I'm more than happy to help and show you pictures of one I've built this way.

Regards

Will
Posted by: Eladi
« on: April 06, 2012, 04:26:47 am »


 Perhaps it would be a good idea insert a choke (low pass audio filter let only pass frequencies below 50 hz.) in vco voltage control that stops the 1khz noise.

 We would have in this way the vco voltage control that don't change so quickly for be interfered for the bf choke.

 It's only an idea don't checked for me. I like the simplicity of this pll design, specially with the programmed chip because unfortunately there is many circuits diagrams publicated but most of them don't publicates the PICs code.

 Sorry for my poor english. Best Regards.
Posted by: DJ Adam Eve
« on: March 01, 2012, 02:04:09 pm »

Please see attache an excel spreadsheet used for looking up frequency using my layout... Pretty straight forward: Either look up frequency on chart OR select from drop down menau and switch setting automatically generated in box on right.

If using open office not that drop down MIGHT not work, in which case simply enter the desired frequency in box.
Posted by: DJ Adam Eve
« on: March 01, 2012, 02:00:53 pm »

OK, If you are at all interested in using my layout you might wnat to wait for a couple of days and i will upload a new image with my additions (which  hopefully reduce the noise to an acceptable level). Failing  that you can always surface mount extra comonents (there's only 3).
Posted by: DJ Adam Eve
« on: February 27, 2012, 12:16:02 pm »

OK... Made some good progress over the weekend.... I probably should state (as i haven't before) that i am using this with my own oscillator/buffer design, and the 2n4427 output design by BW.

I have noticed that Jan fed the PLL signal into the collector in his design, i'm mixing the audio and PLL signal at the VCD and feeding it into the base of an MPSH10 oscillator (NOT the BW type). It may be that this method introduces even MORE noise than Jan's design.

Anyone following this thread please note; there are MUCH better PLL chips out there, the 1057 was designed for 80's fm receivers, look at the date on the datasheet!! Jan himself offers good code and support for a TSA5511 design (lift  it from his 5w tx design to use with other exciters), it also offers momentary push button tuning and LCD display. THere are a few designs for the SAA1057 which also have push button tuning and LCD (Freedo's/Salt and Light/15w multiplex), but ALL will suffer from the same noise problem. There are a couple of Spanish designs which use Jan's PLL and the RDVV oscillator/output which look like they have made some good progress toward minimising the sound by removing the decoupling cap from TCB, however this may lead to stability problems becasue of stray capacitance in the sample and hold circuit.

The secret is definately in the way the control voltage is filtered and used. I am using a voltage follower to isolate the control voltage from the PLL chip itself, this allows me much more scope to play with filter values. I have also changed Jan's code to up the output amp current, something which i THINK Jan reduced in an effort to minimise the noise and current consumption.

I am getting there... slowly!

I will upload pictures of my prototype exciter later.
Posted by: DJ Adam Eve
« on: February 22, 2012, 12:02:34 am »

Oh yeah I have confidence that this pll can work well with your code. Its just a case of figuring out how to filter the output without loading it too much, either that or isolating the pll completely. I will keep you informed. Thanks